1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which the input/output pads of a semiconductor chip and the inner leads of the frame on which the semiconductor chip is mounted are connected electrically by wire bonding or the like.
2. Description of the Prior Art
A typical semiconductor chip has a plurality of input/output pads formed along its edges. In a semiconductor integrated circuit device, those input/output pads and the inner leads arranged on the frame on which the semiconductor chip is mounted are connected electrically, for example, by wire bonding, and this enables the semiconductor chip to communicate electrically with circuits and components arranged outside the package of the semiconductor integrated circuit device.
As shown in FIG. 5, in some conventional semiconductor chips, input/output circuits 42 are arranged in a row along each edge of the semiconductor chip 1, and input/output pads 43 and 44 are arranged in two rows that sandwich the row of input/output circuits 42 from the chip-edge and chip-center sides thereof, with the input/output pads 43 and 44 arranged at regular intervals within each row. This type of pad arrangement is referred to as the "staggered" arrangement in the following description.
As shown in FIG. 9, the semiconductor chip 1 is mounted, by die bonding or the like, on a stage 21 formed on a frame 24. The stage 21 is formed as an island that is supported by support bars 22 at its corners. In each of those areas of the frame 24 which exist between two adjacent support bars 22, a number of inner leads 23 are arranged so as to extend radially.
In this way, for each edge of the semiconductor chip 1, the inner leads 23 are arranged in an area wider than the area in which the input/output pads are arranged. The input/output pads and the inner leads 23 are connected by way of wires 3 (only partially shown in the figure) that are, for example, wire-bonded thereto.
Here, as shown in FIG. 6, to prevent contact between a wire 3f coming from a pad 43 arranged in a chip-center-side (inner) row and a wire 3g coming from a pad 44 arranged in a chip-edge-side (outer) row, the wires 3 are arranged in two, i.e. an upper and a lower, layers. This is the reason that, in the plan view shown in FIG. 9, some wires from pads in an inner row appear to intersect wires from pads in an outer row as indicated at 60, but actually this is not the case.
As shown in FIG. 7, in other conventional semiconductor chips, input/output pads 45 are arranged in one row along each edge of the semiconductor chip 1. In this type of semiconductor chip 1, the input/output pads 45 are connected to input/output circuits 42 by way of a fan-like pattern of metal conductors 51 extending from the input/output circuit 42.
In addition, as shown in FIG. 8, the wires 3h connecting the input/output pads 45 to inner leads 23 are arranged in one layer. Accordingly, in this case, apparent intersection between wires as observed at 60 in FIG. 9 never occurs. Note that, in FIGS. 5 and 7, reference numeral 50 represents conductor layers that are laid over the input/output circuits 42 so as to serve as power-source and ground conductors.
In the former "staggered" arrangement (see FIG. 5), the wires are arranged in two layers as shown in FIG. 6. This inevitably requires that the semiconductor integrated circuit device have a thicker package. This is disadvantageous because a semiconductor integrated circuit device with a thick package is not fit for use in a small-size appliance such as a portable telephone.
On the other hand, in the latter "one-row" arrangement in which the input/output pads are arranged in one row (see FIG. 7), the current wire bonding technique requires that the interval s between two adjacent pads 45 be greater than the width t of each input/output circuit 42. This means that, as long as the pads 45 are arranged in one row, the minimum size of the entire semiconductor chip 1 depends on the total number of pads 45 that are arranged thereon and the intervals. This imposes a limit to the maximum number of pads that can be arranged on a semiconductor chip of a given chip size, and thus it has been impossible to arrange a large number of pads without accordingly increasing the chip size.